Chipforge AI / Domain training
Training looks healthy. The benchmark gets worse.
Investigating CPT and SFT regressions in an RTL model with reproducible VerilogEval runs and controlled experiments.
The problem
At Chipforge AI, Avinash's domain-model work encountered repeated CPT and SFT regressions despite stable training curves. Lower training loss was not translating into better RTL generation.
The work
- Built reproducible VerilogEval evaluation for the baseline and trained checkpoints, making regressions visible outside the training dashboard.
- Used controlled runs to investigate data quality, domain mismatch and training-recipe effects rather than treating every regression as a hyperparameter problem.
- Debugged EOS handling, sequence packing and data-pipeline issues while extending training context from 1K to 8K tokens on NVIDIA DGX infrastructure.
- Designed the next data stage around teacher-distilled examples checked through compilation, simulation and formal verification.
Where the work stands
This is ongoing domain-model research through Asthra. Reproducible checkpoint evaluation and controlled comparisons now support the investigation; tool-verified synthetic data is the next stage of the roadmap.